1. Field of the Invention
Generally, the present disclosure relates to sophisticated integrated circuits including advanced transistor elements that comprise gate structures including a metal-containing electrode and a high-k gate dielectric.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires a large number of circuit elements to be formed on a given chip area according to a specified circuit layout, wherein field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for many types of complex circuitry, including field effect transistors, CMOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, CMOS technology, millions of transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface defined by highly doped regions, referred to as drain and source regions, and a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially affects the performance of MOS transistors. Thus, as the speed of creating the channel, which depends on the conductivity of the gate electrode, and the channel resistivity substantially determine the transistor characteristics, the scaling of the channel length, and associated therewith the reduction of channel resistivity and reduction of gate resistivity, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
Presently, the vast majority of integrated circuits are fabricated on the basis of silicon due to the substantially unlimited availability thereof, the well-understood characteristics of silicon and related materials and processes and the experience gathered over the last 50 years. Therefore, silicon will likely remain the material of choice in the foreseeable future for circuit generations designed for mass products. One reason for the importance of silicon in fabricating semiconductor devices has been the superior characteristics of a silicon/silicon dioxide interface that allows reliable electrical insulation of different regions from each other. The silicon/silicon dioxide interface is stable at high temperatures and, thus, allows the performance of subsequent high temperature processes, as are required, for example, for anneal cycles to activate dopants and to cure crystal damage without sacrificing the electrical characteristics of the interface.
For the reasons pointed out above, in field effect transistors, silicon dioxide is preferably used as a base material for a gate insulation layer that separates the gate electrode, frequently comprised of polysilicon, from the silicon channel region. In steadily improving device performance of field effect transistors, the length of the channel region has been continuously decreased to improve switching speed and drive current capability. Since the transistor performance is controlled by the voltage supplied to the gate electrode to invert the surface of the channel region to a sufficiently high charge density for providing the desired drive current for a given supply voltage, a certain degree of capacitive coupling, provided by the capacitor formed by the gate electrode, the channel region and the silicon dioxide disposed therebetween, has to be maintained. It turns out that decreasing the channel length requires an increased capacitive coupling to avoid the so-called short channel behavior during transistor operation. The short channel behavior may lead to an increased leakage current and to a pronounced dependence of the threshold voltage on the channel length. Aggressively sealed transistor devices with a relatively low supply voltage and thus reduced threshold voltage may suffer from an exponential increase of the leakage current due to the required enhanced capacitive coupling of the gate electrode to the channel region that is accomplished by decreasing the thickness of the silicon dioxide layer. For example, in high performance transistors, a channel length of approximately 0.08 μm may require a gate dielectric made of silicon dioxide as thin as approximately 1.2 nm. Although, generally, usage of high speed transistor elements having an extremely short channel may be restricted to high speed signal paths, whereas transistor elements with a longer channel may be used for less critical signal paths, the relatively high leakage current caused by direct tunneling of charge carriers through an ultra-thin silicon dioxide gate insulation layer may reach values for an oxide thickness in the range of 1-2 nm that may no longer be compatible with requirements for many types of integrated circuits.
Therefore, replacing silicon dioxide, or at least a part thereof, as the material for gate insulation layers has been considered. Possible alternative dielectrics include materials that exhibit a significantly higher permittivity so that a physically greater thickness of a correspondingly formed gate insulation layer nevertheless provides a capacitive coupling that would be obtained by an extremely thin silicon dioxide layer. It has thus been suggested to replace silicon dioxide with high permittivity materials, such as tantalum oxide (Ta2O5), strontium titanium oxide (SrTiO3), hafnium oxide (HfO2), HfSiO, zirconium oxide (ZrO2) and the like.
When advancing to a sophisticated gate architecture based on high-k dielectrics, additionally, transistor performance may also be increased by providing an appropriate conductive material for the gate electrode to replace the usually used polysilicon material, since polysilicon may suffer from charge carrier depletion at the vicinity of the interface to the gate dielectric, thereby reducing the effective capacitance between the channel region and the gate electrode. Thus, a gate stack has been suggested in which a high-k dielectric material provides enhanced capacitance even at a less critical thickness compared to a silicon dioxide layer, while additionally maintaining leakage currents at an acceptable level. On the other hand, a conductive metal-containing non-polysilicon material, such as titanium nitride and the like, may be formed so as to directly connect to the high-k dielectric material, thereby substantially avoiding the presence of a depletion zone. Since the threshold voltage of the transistors is significantly affected by the work function of the gate electrode material that is in contact with the gate dielectric material, an appropriate adjustment of the effective work function with respect to the conductivity type of the transistor under consideration has to be guaranteed, as the well-established way of adjusting the work function by appropriately doping a polysilicon material is no longer available.
For example, appropriate metal-containing gate electrode materials, such as titanium nitride and the like, may frequently be used in combination with appropriate metal species, such as lanthanum, aluminum and the like, to adjust the work function to be appropriate for each type of transistor, i.e., N-channel transistors and P-channel transistors, which may, in some approaches, require an additional band gap offset for the P-channel transistor. For this reason, it has been proposed to appropriately adjust the threshold voltage of some transistor devices by providing a specifically designed semiconductor material at the interface between the gate dielectric material and the channel region of the transistor device, in order to appropriately “adapt” the band gap of the specifically designed semiconductor material to the work function of the metal-containing gate electrode material, thereby obtaining the desired low threshold voltage of the transistor under consideration. Typically, a corresponding specifically designed semiconductor material, such as silicon/germanium and the like, may be provided by an epitaxial growth technique at an early manufacturing stage, which may also present an additional complex process step, which, however, may avoid complex processes for adjusting the work function and thus the threshold voltages in a very advanced process stage.
It turns out, however, that the manufacturing sequence of forming the threshold adjusting semiconductor alloy may have a significant influence on the overall process flow, as will be described in more detail with reference to FIGS. 1a-1f. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 that comprises a substrate 101, above which is formed a silicon-based semiconductor material 102 having an appropriate thickness for forming therein and thereabove transistor elements. An isolation structure 102C is formed in the semiconductor layer 102 and laterally delineates and thus forms active regions 102A, 102B. In this context, an active region is to be understood as a semiconductor material in which an appropriate dopant profile is to be created in order to form PN junctions for one or more transistors. In the example shown, the active region 102A corresponds to a P-channel transistor, while the active region 102B corresponds to an N-channel transistor. Hence, the active regions 102A, 102B comprise an appropriate basic dopant concentration in order to determine the basic conductivity of a P-channel transistor and an N-channel transistor, respectively. Furthermore, in the manufacturing stage shown, a mask layer 103 is formed on the active regions 102A, 102B in the form of a silicon dioxide material. Furthermore, an etch mask 104 is provided such that the active region 102B is covered, while the active region 102A, i.e., the mask layer 103 formed thereon, is exposed to an etch ambient 105.
The semiconductor device 100 as illustrated in FIG. 1a may be formed on the basis of the following process strategies. The isolation structure 102C is formed on the basis of well-established lithography, etch, deposition, planarization and anneal techniques, in which, for instance, a trench is formed in the semiconductor layer 102 on the basis of a lithography process, which is subsequently filled with an appropriate insulating material, such as silicon dioxide, silicon nitride and the like. After removing any excess material and planarizing the surface topography, the processing is typically continued by performing a plurality of implantation sequences using an appropriate masking regime in order to introduce the required well dopant species for generating the basic dopant concentration in the active regions 102A, 102B in accordance with requirements of the transistors to be formed. After activating the dopant species and re-crystallizing implantation-induced damage, the processing is continued by forming the mask layer 103 on the basis of for instance, an oxidation process, followed, by the deposition of a mask material, such as a resist material, that is subsequently patterned into the mask 104 by well-established lithography techniques. Next, the etch process 105 is performed, for instance using a wet chemical etch recipe based on hydrofluoric acid (HF), which is a very efficient chemical for removing silicon dioxide material selectively with respect to silicon material.
FIG. 1b schematically illustrates the semiconductor device 100 after the above-described process sequence and after removal of the etch mask 104 (FIG. 1a). The etch process 105 (FIG. 1a) is typically performed in an appropriate chemical reactor in which a plurality of substrates may be concurrently processed, wherein the wet chemical etch chemistry may also be provided at the back side (not shown) of the substrate 101, thereby also efficiently removing any oxide material which may have been formed upon providing the mask material 103. Upon exposure of the active region 102A, the device 100 may be prepared for a subsequent selective epitaxial growth process for forming a silicon/germanium alloy on the active region 102A.
FIG. 1c schematically illustrates the semiconductor device 100 when exposed to a further process ambient 106 upon preparing the device 100 for the selective epitaxial growth process. Typically, the process ambient 106 is established in the deposition reactor by applying elevated temperatures and appropriate reactive gas components in order to remove any further contaminants and oxide residues from the exposed surface areas of the active region 102A, which may still be present in the form of a native oxide and the like. During the process 106, a thickness of the mask layer 103 may be reduced, while nevertheless maintaining a significant portion so as to mask the active region 102B.
FIG. 1d schematically illustrates the semiconductor device 100 during a selective epitaxial growth process 108 in which process parameters are selected such that a significant material deposition is restricted to the exposed active region 102A, while a material deposition on a silicon dioxide surface area, such as the surface of the isolation structure 102C and the mask layer 103, is strongly suppressed. For this purpose, the flow rates, the pressure, the temperature and the like may be selected in accordance with well-established selective epitaxial growth recipes in order to obtain a desired high deposition selectivity with respect to silicon and silicon dioxide surfaces. Thus, during the selective epitaxial growth process 108, a silicon/germanium alloy 109 is selectively formed on the active region 102A, thereby providing a semiconductor material having a different band gap compared to the silicon-based material of the active region 102A. Generally, the material composition of the alloy 109, as well as the thickness thereof, has a strong influence on the finally obtained threshold voltage of the P-channel transistor to be formed in and above the active region 102A. For example, in sophisticated applications, a target thickness of the silicon/germanium alloy 109 is in the range of approximately 8-50 nm, wherein a thickness variation of several percent may result in a significant variability of the finally achieved transistor characteristics. Moreover, since the transistor characteristics may also be strongly influenced by the further processing, for instance by forming a high-k dielectric material in combination with a metal-containing electrode material, in particular when adjusting the critical work function of the resulting electrode material, any process irregularities, such as contamination and the like, may also significantly affect transistor performance and device uniformity.
FIG. 1e schematically illustrates the semiconductor device 100 when exposed to an etch ambient 110 in which the mask 103 (FIG. 1d) is removed selectively with respect to the active region 102B and selectively to the active region 102A, which may now comprise the threshold adjusting semiconductor alloy 109. The etch process may be performed on the basis of hydrofluoric acid, which may be applied in a chemical reactor, as discussed above, thereby efficiently removing silicon oxide-based material from the semiconductor layer 102 and any other exposed surface areas, such as the back side of the substrate 101 and the like.
FIG. 1f schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage. As illustrated, a first gate electrode structure 160A is formed on the active region 102A, i.e., on the threshold adjusting semiconductor alloy 109, and comprises a gate dielectric material 161A in combination with a conductive metal-containing electrode material 162A. Moreover, a further electrode material 163, for instance in the form of a silicon material, may be provided, possibly in combination with a dielectric cap material 164. Similarly, a second gate electrode structure 160B is formed on the active region 102B and comprises a gate dielectric material 161B in combination with a metal-containing electrode material 162B. Furthermore, the gate electrode structure 160B may also comprise the electrode material 163 and the dielectric cap material 164. The gate electrode structures 160A, 160B may have a gate length, i.e., in FIG. 1f, the horizontal extension of the electrode materials 162A, 162B, respectively, which may be 50 nm and less, depending on the overall design requirements. Furthermore, it should be appreciated that the gate dielectric material 161A may basically have the same configuration as the gate dielectric material 161B, while, in some cases, an additional work function adjusting species, such as aluminum, lanthanum and the like, may be incorporated so as to provide the desired electronic characteristics of a transistor 150A or a transistor 150B, respectively. Similarly, the metal-containing electrode materials 162A, 162B may have basically the same configuration in some approaches, for instance these materials may be provided in the form of titanium nitride and the like, while, in other cases, a work function metal species may be incorporated therein so that the materials 162A, 162B may differ in their material composition so as to obtain a different desired work function for the transistors 150A, 150B.
The semiconductor device 100 as shown in FIG. 1f may be formed on the basis of a complex process sequence in which appropriate materials for the gate dielectric material 161A, 161B may be formed, for instance, by oxidation in combination with deposition techniques and the like. For example, a very thin silicon oxide based material may be provided so as to act as an efficient interface material, followed by a high-k dielectric material, such as hafnium oxide and the like. Thereafter, appropriate work function metal species may be deposited and patterned, possibly in combination with any heat treatment for diffusing appropriate species towards and into the dielectric material, thereby forming the gate dielectric layers 161A, 161B having included therein different types of work function species. In other cases, the work function metals may be provided as distinct layers above the gate dielectric materials and may thus represent a portion of the metal-containing electrode materials 162A, 162B. Thereafter, the electrode material 163 may be deposited, for instance, in the form of amorphous silicon and the like, followed by the deposition of the dielectric cap material 164, possibly in combination with other materials, such as hard mask materials, anti-reflective coating (ARC) materials and the like. Next, the complex gate layer stack may then be patterned by applying sophisticated lithography and etch techniques in order to obtain the gate electrode structures 160A, 160B. It should be appreciated that the finally achieved electronic characteristics of the gate electrode structures 160A, 160B may depend on the material composition of the various material and the uniformity of the corresponding deposition, lithography and etch processes.
Thereafter, the processing is continued by forming drain and source regions, which may be preceded by the incorporation of a strain-inducing semiconductor alloy in one or both of the active regions 102A, 102B, if required. The drain and source regions may typically be formed by ion implantation on the basis of an appropriate spacer structure to be formed on sidewalls of the gate electrode structures 160A, 160B. Finally, metal silicide regions may be formed in the drain and source areas and in the electrode material 163, thereby completing a basic transistor configuration using the sophisticated high-k metal gate electrode structures 160A, 160B. It turns out, however, that the resulting transistor elements 150A, 150B may suffer from an increased variability in transistor characteristics, such as threshold variability and the like, which may thus significantly reduce production yield for sophisticated semiconductor devices requiring a high-k metal gate electrode structure.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.